1. Field of the Invention
The present invention relates to a power ON reset circuit, and, more particularly to a power ON reset circuit which is suitable for a reset power supply circuit of a microcomputer constituted of CMOS transistors.
2. Description of the Related Art
A microcomputer has many sequential circuits typified by flip-flops. The sequential circuit looses its one stable status once powered off, and will have a so-called unstable status of either a logical value of "0" or "1" when powered on next time. This is called "volatile." A RAM (Random Access Memory) is well known to show this feature most prominently.
For a microcomputer to execute a predetermined operation immediately after power on, the statuses of at least some sequential circuits should always be the same immediately upon power on. In a micro-coded microcomputer, for example, it is necessary to always access the address of the same micro ROM (Read Only Memory) immediately after power on.
To set the status of the sequential circuit, which should always be the same upon power on, immediately after power is given, is called "initialization" or "system reset." This system reset has conventionally been executed using a circuit which outputs a pulse of a given width upon power on. This circuit is called a "power ON reset circuit."
FIG. 1 is a circuit diagram showing an example of a conventional power ON reset circuit. A series circuit of a P channel MOS type FET (Field Effect Transistor) M1 and a resistor R1 is connected between a power supply of voltage VDD and ground, with the FET M1 connected to the power supply (VDD). The gate of the FET M1 is connected to a node N1 between the FET M1 and the resistor R1.
Also connected between the power supply (VDD) and ground is a series circuit of a resistor R2 and an NMOSFET M2, with the FET M2 connected to the ground. The gate of the FET M2 is connected to the node N1, with a capacitor C1 connected between the node N1 and the ground potential.
A series circuit of CMOSFETs M3 and M4 is connected between the power supply (VDD) and ground, with the FET M4 connected to the power supply (VDD). The gates of the FETs M3 and M4 are both connected to a node N2 between the resistor R2 and the FET M2. A capacitor C2 is connected between the supply voltage VDD and the node N2 (the gates of the FETs M3 and M4).
Connected to the subsequent stage of the CMOSFETs M3 and M4 are CMOSFETs M5 and M6 having the same structure as the FETs M3 and M4. The gates of the CMOSFETs M5 and M6 are connected to a node N3 between the FETs M3 and M4. The gates of the FETs M5 and M6 are connected via a capacitor C3 to the ground potential. A node N4 is where the FET M5 is connected to the FET M6.
The input terminals and output terminals of the CMOSFETs M3 and M4 are the node N2 and the node N3 respectively, while the input terminals and output terminals of CMOSFETs M5 and M6 are the node N3 and the node N4, respectively.
This circuit outputs a high pulse which is reset when the power supply voltage VDD rises to a predetermined potential from the ground (GND) potential. This function is accomplished by the capacitors C1 and C3 connected at one end to the GND and the capacitor C2 connected to the power supply of voltage VDD. When the power is given from the power supply (VDD), those capacitors C1, C3 and C2 are not charged so that the nodes N1, N2 and N3 are at the same potential levels as the power supply voltage VDD and GND. But, the output of the node N4 becomes a high level (potential nearly equal to the supply voltage VDD) first, after which the capacitors C1-C3 are charged in order and the potentials at the nodes N1, N2 and N3 become the potentials of the (VDD-.vertline.VTM1.vertline.), GND and VDD. As a result, the output of the node N4 becomes a low level (about the GND potential). VTM1 is the threshold voltage of the FET M1.
As the output of the node N4 becomes a low level, VDD-.vertline.VTM1.vertline. should be higher than the logical threshold voltage of an inverter comprising the FET M2 and the resistor R2.
It is apparent from the above that the circuit which merely outputs a reset pulse upon power on can be accomplished by a simple structure having PMOSFETs M7 and M9, an NMOSFET M8 and a capacitor C4 as shown in FIG. 2. In FIG. 2, the FET M7 and the capacitor C4 are connected in series between the power supply of voltage VDD and ground, while the PMOSFET M9 and NMOSFET M8 are connected in series therebetween. The gates of the FETs M9 and M8 are both connected to a node N5 where the FET M7 is connected to the capacitor C4, with the gate of the FET M7 grounded. A node N6 where the FET M9 is connected to the FET M8 is the output terminal of this circuit.
Referring to FIG. 2, as the capacitor C4 has not been charged immediately after power from the supply voltage VDD is given, the node N5 becomes a low level and the output of the node N6 becomes a high level. If the potential of the power supply voltage VDD is higher than the absolute value of the threshold voltage of the FET M7 thereafter, the FET M7 is turned on, causing the capacitor C4 to be charged up. As a result, the nodes N5 and N6 respectively become a high level and a low level.
The power ON reset circuit shown in FIG. 1 has an advantage over the circuit shown in FIG. 2 in that the former circuit also has the function of a voltage detector. Even if the VDD potential falls after the supply voltage VDD rises once and the output of the node N5 becomes a low level in the circuit in FIG. 2, the node N6 stays low and there is no way to know that the VDD potential has dropped.
According to the circuit in FIG. 1, from a viewpoint of DC current, when the potential of the power supply voltage VDD becomes higher than .vertline.VTM1.vertline.+VTM2 (VTM2: threshold voltage of the FET M2), the output of the node N4 becomes a low level while when the VDD potential becomes lower than .vertline.VTM1.vertline.+VTM2, the output of the node N4 becomes a high level, thus making it possible to detect whether the power supply voltage VDD is higher or lower than .vertline.VTM1.vertline.+VTM2. This is because that as the gate and drain of the FET M1 are short-circuited, the potential at the node N1 becomes VDD-.vertline.VTM1.vertline. and the potential at the node N2 changes from a high level to a low level when VDD-.vertline.VTM2.vertline. becomes higher than the logical threshold voltage of the inverter which comprises the FET M2 and the resistor R2. That is, the potential at the node N4 is a low level when the value of A expressed by the following relationship is positive: A=VDD-.vertline.VTM1.vertline.-(the logical threshold value of the inverter having the FET M2 and resistor R2). Conversely, the potential at the note N4 is a high level when the value of A is negative.
As the load of the inverter comprising the FET M2 and the resistor R2 has a constant resistance R2, the logical threshold value of this inverter is around the threshold voltage of the FET M2 whose current varies greatly. Accordingly, when VDD-.vertline.VTM1.vertline.-VTM2=VDD-(.vertline.VTM1.vertline.+VTM2) is positive, the output of the node N4 in the power ON reset circuit in FIG. 1 becomes a low level, while the former potential is negative, the output of the node N4 becomes a high level, so that the positive or negative difference between VDD and .vertline.VTM1.vertline.+VTM2 will be detected. It is of course possible to adjust the detection voltage by the resistances of the resistors R1 and R2 and (gate width)/(gate length) of the FETs M1 and M2.
In general, a power ON reset circuit which, like the one shown in FIG. 1, can also detect the DC supply voltage is incorporated in the microcomputer that is used in battery-driven devices, such as portable devices. This power ON reset circuit allows the microcomputer to inform a user of a low battery or stops the microcomputer before it crashes due to the battery voltage dropping below the proper operational voltage range.
Due to the recent widening application of microcomputers to various types of portable devices, fast operation of microcomputers is often demanded in battery-driven devices. The operational voltage range therefore becomes narrower, demanding for a power ON reset circuit which can detect the supply voltage more accurately.
Since the detection voltage of the conventional power ON reset circuit in FIG. 1 depends on (VTM1+VTM2), this circuit has a large manufacturing variation and is temperature dependent. As the threshold voltage of MOSFETs normally has a manufacturing variation of .+-.0.1 to .+-.0.2 V and a temperature dependency of around -2 mV/.degree. C., (VTM1+VTM2) has a temperature variation of .+-.0.2 to .+-.0.4 V normally, and about .+-.0.2 V with the operational temperature range set to .+-.50.degree. C. The difference between the maximum and minimum values of the detection voltage therefore becomes 0.8 to 1.2 V.
A band-gap reference voltage generator is well known as having a high voltage precision. FIGS. 3 and 4 illustrate two typical examples of the conventional band-gap reference voltage generator which uses MOSFETs. The anode area is determined so that the saturated currents IS1, IS2 and IS3 of PN junction diodes D1, D2 and D3 have a relation of IS1=IS3&gt;IS2. The ratio of the resistance of a resistor R3 to that of a resistor R4 is set to a predetermined value according to the output voltage. For easier explanation, it is assumed below that ratio R4/R3=n (n: positive integer).
In the circuit in FIG. 3, a diode D1, a resistor R3 and CMOSFETs M10 and M11 are connected in series, a diode D2, and CMOSFETs M12 and M13 are connected in series, with the gates of the FETs M11 and M13 connected together and the gates of the FETs M10 and M12 connected together, and a diode D3, a resistor R4 and PMOSFET M14 are connected in series, with the gate of the FET M14 connected to the gates of the FETs M11 and M13. The VDD side end of the resistor R3 is a node N10, the anode of the diode D2 is a node N11, and the VDD side end of the resistor R4 is a node N12 which is the output terminal of this circuit.
The circuit in FIG. 4 has a comparator 7 which has the node N10 as a positive (+) input 8 and the node N11 as a negative (-) input 9 and has its output coupled to the gate of the FET M14. This circuit does not have the FETs M10 and M12 of the circuit shown in FIG. 3. Except for those points, the circuit in FIG. 4 is the same as the circuit in FIG. 3. Therefore, the same reference numerals as used in FIG. 3 are also used in FIG. 4 to denote the identical or corresponding components, and their detailed explanation will not be repeated.
The PMOSFETs M11, M13 and M14 have the same ratio of (gate width)/(gate length) and NMOSFETs M10 and M12 also have the same (gate width)/(gate length).
The operations of those circuits will now be discussed. In FIGS. 3 and 4, the constant current flows through the FETs M11, M13 and M14, and the current value is determined so that the potentials at the nodes N10 and N11 become equal to each other. When the same current flows through the FETs M10 and M12, their gate-source voltages should be the same, because the FETs M10 and M12 have the same (gate width)/(gate length) ratio. With the gates of the FETs M10 and M12 short-circuited, therefore, the potentials at the nodes N10 and N11 where the sources of those transistors are connected become equal to each other. In FIG. 4, the potentials at the nodes N10 and N11 are compared with the comparator 7 and are so controlled as to be equal to each other. Thus, the following equation is derived. EQU I.times.R3+VT.times.ln(I/IS1)=VT.times.ln(I/IS2)
where I is the current flowing through the FETs M11, M13 and M14 and VT=kT/q (k: Boltzmann's constant, T: absolute temperature and q: unit charge). Thus, I is given by the following equation (1). EQU I=VT.times.ln(IS1/I2).times.1/R3 (1)
The output voltages of the nodes N12 and N13 both become the voltage across the resistor R4, which is given by the following equation (2), plus the forward voltage across the diode D3. EQU R4.times.VT.times.ln(IS1/IS2).times.1/R3=n.times.VT.times.ln(IS1/IS2)(2)
The equation (2) is determined by the resistance ratio n, the ratio of the anode area of the diode D1 to that of the diode D2, and the absolute temperature T. Generally speaking, the area ratio of the resistors, the PN junction, and etc. is obtained at high precision by the MOS processing technology, so that the output voltage given by the equation (2) becomes a constant value very accurately at a constant temperature.
As the absolute value of the forward voltage of diodes normally has a slight variation of less than about .+-.20 mV at a constant temperature, the output voltages at the nodes N12 and N13 are approximately constant at the same temperature and are about 1.1 to 1.2 V at the normal temperature.
While the voltage across the resistor R4 has a positive temperature dependency with respect to the absolute temperature T as apparent from the equation (2), the forward voltage of diodes has a negative temperature dependency. The temperature characteristic can therefore become considerably small by properly selecting n in the equation (2).
FIG. 5 shows a circuit which uses a circuit 14 similar to the one shown in FIG. 3 or FIG. 4, in addition to a comparator 16 and resistors R5 and R6. This circuit can accurately detect the power supply voltage of an arbitrary value by selecting the proper resistances for the resistors R5 and R6. Thus, the circuit in FIG. 5 is expected to be adapted for a power ON reset circuit. The circuit in FIG. 5 however has two critical shortcomings as a power ON reset circuit.
First, the circuits shown in FIGS. 3 and 4 do not properly function by simply activating the power supply (VDD) because the state of no current flowing through the FETs M11 and M13 before power on will be satisfied in those circuits even after the power supply (VDD) is activated. The requirements for the circuits in FIGS. 3 and 4 are such that the same current should flow through both the FETs M11, M13 and M14, and also through the FETs M10 and M12, and that the potentials at the nodes N10 and N11 should be equal to each other. The state of no current flowing through the FETs M11 and M13 fulfills the requirements.
As a solution to this problem, a capacitor C5 is connected to a node N14 in the circuit in FIG. 3, and a capacitor C6 is connected to a node N15 in the circuit in FIG. 4, as shown in FIGS. 6 and 7, respectively. With this modification, upon power on, the PMOSFETs M11 and M13 are always turned on to permit a current to flow therethrough, and the modified circuits will properly start functioning. This modification, however, has the following shortcoming. Given that VGSM11 represents the potential difference between the gate and source of each of the FETs M11 and M13 under the proper operation, when VDD drops abruptly by .vertline.VGSM11.vertline.-max(.vertline.VTM1.vertline., .vertline.VTM3.vertline.), the FETs M11 and M13 are turned off and the current flowing through those FETs M11 and M13 becomes 0 (max (a, b) representing a larger one of a and b). Even if the supply voltage VDD is above the designed detection voltage, the modified circuits still have the same power-on problem as the circuit without the capacitor C5 or C6 has.
The second critical shortcoming is that the modified circuits would malfunction when the supply voltage falls down to or below a certain level. To provide the expected output voltage, all the MOSFETs in the circuit in FIG. 3, the FETs M10 to M14, should operate in the saturated area. In view of the series connection of the diode D2 and FETs M12 and M13, this requires a supply voltage equal to or above EQU 0.1 V+VTM12+VFD2 (3)
where VTM12 is the threshold voltage of the FET M12 which is normally about 0.7 V, VFD2 is the forward voltage of the diode D2, normally about 0.5 to 0.7 V, and the first term, 0.1 V, is the minimum voltage necessary to saturate the FET M13.
The voltage expressed by the equation (3) is therefore normally 0.3 to 1.5 V below which the output of the node N12 rapidly drops, setting a low level in the circuit in FIG. 3 as in the case where the supply voltage is sufficiently high. When the supply voltage becomes below the operational voltage of the comparator 7, the circuit in FIG. 4 naturally malfunctions. Normally, the minimum operational voltage of a comparator designed by the CMOS processing technology to function on a low voltage is about 1.5 to 1.8 V. The power ON reset circuit shown in FIG. 1 does not have the above-described two problems inherent to the circuit in FIG. 5 which is designed based on the circuit in FIG. 3 or FIG. 4. In this respect, the power ON reset circuit in FIG. 1 having a large variation in detection voltage has conventionally been used in a microcomputer.
While the conventional power ON reset circuit in FIG. 1 surely outputs a reset pulse upon power on, it has a large variation in DC detection voltage, so that the voltage allowable by the entire microcomputer-based system should be the minimum operational voltage of microcomputers plus a voltage variation of the power ON reset circuit. In other words, while this conventional circuit can control the crashing of microcomputers, it inevitably requires an increased minimum operational voltage.